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Mentor Graphics Corporation, the market leader in printed circuit board (PCB) design software, and Altera Corporation, a leading supplier of programmable logic devices (PLDs), today jointly announced support for the STAMP timing file format, allowing PLD and PCB designers to easily share PLD timing data for efficient board-level timing analysis.

Mentor Graphics also announced the availability of the Tau® version 2.3 tool. Tau is the only timing analysis tool developed specifically for board verification. Tau 2.3 offers enhanced usability through additional analysis feedback features with continued support for PLDs with the STAMP interface format.

The need for common data formats between PLD and PCB designers is driven by the continued increase in the use of complex, high-speed PLDs, especially in the networking and communications industries in which time-to-market is particularly critical. In addition, as the complexity and speed of both PLDs and PCBs continues to increase, quick, accurate board-level timing analysis allowed by the standard timing data interface is essential.

Altera has added STAMP interface support to the latest version of its PLD design toolset, Quartus™ II development software. The Quartus II development software will now output component timing information in the STAMP standard format, part of the Liberty™ open source library format from Synopsys, which can be used by Tau, Mentor's board-level timing analysis tool, to quickly create Tau timing models.

"With high-density, high-speed PLDs at the core of many of today's system designs, verifying board-level timing is critical to ensuring reliable system operation early in the design cycle," said Henry Potts, general manager and vice president, Systems Design Division, Mentor Graphics. "This joint effort with Altera will clearly benefit our mutual customers with a common data interface for timing analysis and verification."

"Our new products are pushing the performance envelope. The new Mercury programmable ASSP device family offers data rates of up to 1.25 Gbps and a total CDR bandwidth of up to 45 Gbps which makes board level verification critical," said Tim Colleran, Altera vice president of product marketing. "By allowing easy data transfer between Altera's Quartus II development software and Mentor's Tau product, we can really enhance the design verification process."

New Enhancements in Tau 2.3
Tau, the industry's only comprehensive board-level timing analysis solution, uses symbolic timing analysis to automatically eliminate reporting of false timing problems that can occur when traditional static timing analysis tools are used at the board level.

Tau 2.3 includes several new features designed to make the tool easier to use. The latest version offers an enhanced user interface for model selection, compilation, and block diagram viewing with greater interoperability support.

About STAMP
Synopsys' open source library format, Liberty™, includes both .lib and STAMP representations. Liberty is supported by more than 60 semiconductor vendors with more than 500 submicron libraries, and more than 30 EDA vendors supply over 75 production tools utilizing the current open source release of Liberty. It has evolved over more than 13 years, driven by tool technology and library modeling needs, and continues to be regularly updated via an aggressive open source model.

About Quartus II Development Software
Altera's Quartus II software delivers superior designer productivity and supports system-level designs with features including the PowerFit™ fitter technology, support for multi-million gate devices, and integration with third party tools. Also, with support for the Excalibur™ embedded processor family, it extends the user scope beyond hardware by including a software workflow that offers C/C++ compilers and debuggers in a fully integrated development environment. The Quartus II software supports major operating systems, including Windows 2000, Windows NT, Windows 98, Sun Solaris, and HP-UX.

About Altera
Altera Corporation (Nasdaq: ALTR), The Programmable Solutions Company®, was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. More information on Altera is available on the