Product/Service


MAJICPLUS : Multi-processor Advanced JTAG Interface Controller with Trace

Source: Embedded Performance, Inc. (EPI)
Ideal for SoC-based applications
Details

MAJICPLUS Development System Features:
  • Ideal for SoC-based applications
  • 32 x 512K trace memory with trace control
  • Non-intrusive, uses no target resources
  • Execution tracing from embedded flash, ROM, or cache
  • Supports a wide choice of on-chip debug interfaces
  • Supports a wide variety of CPU cores
  • Supports on-chip hardware breakpoints
  • Unlimited software breakpoints
  • Programmable JTAG Clock (TCK = 0 to 40 MHz)
  • Programmable trigger-in and trigger-out connections
  • Ethernet and Serial I/O Ports for fast, flexible host interface
  • High-speed download (>200k bytes per second) of application code
  • Internal RISC Processor assures fast operation
  • Flash Memory for easy firmware updates to support additional CPU cores or on-chip debug interfaces
  • Sleep-mode support
  • LEDs display operation status
  • Open API for debugger interface

    Product Information
    The MAJICPLUS emulator provides a high-speed hardware interface between processors with an on-chip debug interface and industry standard debuggers. It is available with a choice of EPI debuggers and may be adapted for use with RT/OS-aware debuggers from leading RT/OS vendors. The unit is self-contained, in a small case approximately 2 inches x 6 inches x 7 inches in size.
    Now, engineers using SoC devices can have the same level of control and visibility of the embedded CPU operations as they would with in-circuit emulators in traditional discrete CPU designs. The result is faster software integration, better testing, and improved time to market. The MAJIC's ability to expand to support additional cores, debug interfaces, or SoC devices eliminates the need to buy new emulators for each new project, thus reducing project costs.
    Completely non-intrusive, the MAJICPLUS communicates to the CPU core by JTAG using the existing boundary scan pins. It uses no target memory and requires no porting to the target system.
    Complete processor control means you can start, stop and single-step execution; read and write to registers, memory, and system I/O; and download code to target RAM - all within most industry standard debugger interfaces.

    Complete visibility means that you can now trace program execution on the deeply embedded CPU core. Using on-chip debug facilities such as PCTrace, N-Trace and Real Time Debug, the emulator provides real-time visibility into the program's behavior even when the CPU is executing from cache, flash or ROM embedded with an SoC.
    You may adapt the MAJICPLUS for plug-and-play operation with your specific processor or CPU core by selecting from a wide range of configuration kits. The kits contain the firmware and user license to match your CPU's on-chip debug facilities. Install multiple configuration kits, and the MAJICPLUS will support a variety of CPU types. The configuration kits also contain the adapters, accessories, and target interconnection cables required for the selected CPU.
    The MAJICPLUS is ready to run with the EPI software tools and any development board that supports a connection to the on-chip debug interface. This combination of tools will work together to provide you with a proven working environment.
    The MAJICPLUS is available as a stand-alone unit or as a complete emulation kit. The kit comes with serial and Ethernet cables, source-level debugger, documentation, and one year of free maintenance, support, and updates. Part number: MAJICPLUS-KIT.
    Full development kits are also available that include a full compilation toolkit. See the MAJIC Price and Configuration Guide for full details of these development kits.

    Embedded Performance, Inc. (EPI), 606 Valley Way, Milpitas, CA 95035-4138. Tel: 408-957-0350; Fax: 408-957-0307.

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