News | April 10, 2001

Proceler to Preview First C-based Soft Processor Design Capability at ESC 2001

At the upcoming Embedded Systems Conference in San Francisco, April 9-13, 2001, Proceler (pronounced Pro' sa lair), Inc., a privately held, venture-capital-backed company, will preview a revolutionary technology that automatically generates high-performance application-specific soft processors from standard C/C++ language code, providing high-performance acceleration for compute-intensive embedded applications, while cutting months off design cycles. Proceler's technology identifies computationally intensive code blocks – such as loops – that are candidates for acceleration. It implements those blocks in reconfigurable logic on an FPGA (field programmable gate array) while compiling the remaining code as a standard executable for a microprocessor. Proceler will be demonstrating an alpha version of this technology. Beta is expected during the summer of 2001, with full product release in the fall of 2001.

"We've gathered an experienced team of hardware and software compiler experts to tackle a challenge – how to intelligently partition a design between hardware and software and how to generate hardware-accelerated processors from a C-level specification," stated Naren Nachiappan, Chief Executive Officer and co-founder of Proceler. "Our technology dramatically changes the way high-performance embedded systems are designed, speeding new accelerated hardware to market in a fraction of the time it now takes. We see applications for this in the competitive networking, wireless, and Internet appliance markets."

Company Background

The name of the company reflects the company's direction – "Pro" from processor or process and "celer" from celerity, meaning speed in accomplishing work or action. Together, these two roots describe the two fundamental aspects of Proceler's technology innovation: 1) the technology builds application-specific "soft" processors that accelerate embedded systems performance, and 2) the technology utilizes an accelerated, software-based development process to build these soft processors.

Naren Nachiappan, CEO, and Dr. Krishna V. Palem, Chief Technology Officer, founded the company as FlexSilicon in October of 1999. Previously at VenturCom, the industry's leading developer of software for Windows-based embedded systems, Nachaippan was the Sr. VP of Business Development, responsible for strategic alliances with Intel, Microsoft and other companies. He was responsible for building VenturCom's Asian distribution channels and directly recruited a majority of the top 25 Japanese manufacturing companies as customers and partners. While VP of Engineering at VenturCom, he was the chief architect of the industry's first and very successful embedded UNIX product, which has been successfully installed in embedded applications worldwide, including several on the Boeing 777. He holds an M.B.A from the Walter A. Haas School of Business at the University of California at Berkeley.

Dr. Palem pioneered the DVAITA concept that underscores Proceler's technology innovations and is responsible for the company's technology strategy. He is a professor and senior research leader at the Georgia Institute of Technology and director of the Center for Research in Embedded Systems and Technologies (CREST), Dr. Palem was previously on the faculty of Computer Science Department and the Courant Institute of Mathematical Sciences at NYU where he founded the Real-time Compilation Technologies and Instruction Level Parallelism Laboratory, the first laboratory of its kind to focus on compilation technologies for embedded systems. Prior to his academic career, he also was a research staff member at the IBM T. J. Watson Research Center and an advanced technology consultant on compiler optimizations at the IBM Santa Teresa Laboratory, where he worked on parallel and optimizing compiler technologies. He has received corporate awards for excellence from IBM, Panasonic and Hewlett-Packard Corporation. Dr. Palem holds a Ph.D. in Computer Engineering and Science from the University of Texas at Austin.

Proceler features a top management team with equally impressive credentials, all of which are explained in detail on the company's web site at Members include: Robert Carrade, Chief Financial Officer; Suresh Cheemalavagu, Vice President of Product Engineering; Dr. Hansoo Kim, Vice President of Compiler Technologies; Rex Melton, Vice President of Marketing; and Dr. Sudhakar Yalamanchili, Vice President of Synthesis and Co-Design Technologies.

The Proceler Technology

The core of Proceler's technology consists of:

1) DVAITATM (Dynamically Variable Instruction seT Architecture), a soft instruction set architecture (ISA) that defines a flexible model for building high-performance, application-specific soft processors. DVAITA is realized by Proceler's soft micro-architecture, a set of modular, pre-synthesized components that implement an instruction set, as well as dataflow and control elements;

2) The DVAITA software platform, which creates application-specific soft processors from C/C++ source code by optimizing the performance of compute-intensive portions of the code; and

3) The Proceler application programming interface (API) and run-time interface, which seamlessly integrates the soft processors on a reconfigurable computing system.

A typical ISA abstracts hardware functional units into instructions and storage resources into registers. More complex ISAs expose other aspects of the datapath that can be scheduled by the compiler. As opposed to these "hard" ISAs that require the implementation of the instructions to be fixed at design time and presented to the compiler in the form of a fixed microprocessor datapath implementation, DVAITA is a soft ISA. DVAITA can include instructions and components customized to a particular application.

The DVAITA software platform creates application-specific soft processors directly from the high-level C/C++ source code. This platform employs a highly innovative compiler that analyzes the code and performs the following five steps:

1) Identifies the computationally intensive code blocks – such as loops – that are candidates for implementation within reconfigurable logic;

2) Applies powerful program analysis, transformation, scheduling, and code generation techniques to the code block;

3) Configures the soft micro-architecture components to create the soft processors;

4) Compiles the remaining code as a standard executable for the microprocessor; and

5) Transparently integrates the microprocessor and soft processor(s) through a run-time interface.

The Proceler run-time interface is portable to alternative real-time operating systems that reside on the microprocessor. The Proceler API allows third parties to integrate Proceler development capabilities into their own development environments.

The Proceler-created soft processors are automatically implemented on reconfigurable computer systems (RCSs). An RCS is a commodity hardware solution that combines a microprocessor with a reconfigurable logic device, such as a field programmable gate array (FPGA), in a bus-based configuration or integrated into one of the new generation of processor architectures called configurable system-on-chip (CSoC) devices.

"Proceler's technology leverages extensive research in compiler technology," stated Dr. Palem. "The research that has produced Explicitly Parallel Instruction Computing (EPIC) architectures has concurrently producedoptimizing compiler technologies that expose, enhance, and exploit instruction-level parallelism. With the realization of DVAITA, an abstraction layer that hides the complexities of logic design, Proceler's next generation compiler technologies can be utilized to build processing solutions customized to the requirements of application software. DVAITA and its software platform enable the generation of an application specific soft processor for the computationally intensive portions of an application and transparently integrates the soft processor with software targeted to the control microprocessor."

Markets for Proceler's Technology

Because Proceler's soft processors accelerate the compute-intensive functions of the embedded application, it's ideal for high-performance applications. Proceler's technology speeds new designs to market, bypassing the lengthy hardware design phase by automatically implementing the accelerated parts of the design in reconfigurable logic. Therefore, it's ideal for highly competitive marketplaces where speed to market is critical for success.

By implementing the designs in reconfigurable logic on an FPGA, Proceler's solution provides maximum system flexibility. The reconfigurable hardware can change to accommodate new features and frequent field upgrades.

Here's how Proceler's technology could be used to create a network router. Proceler's technology automatically partitions the application code, implementing the iterative, compute-intensive operations such as packet-processing as an application-specific soft processor in reconfigurable logic. Proceler's technology also implements the non-compute-intensive functions of the router, such as protocol processing functions, on the RISC microprocessor. Other standard software components, such as the administrative user interface, can be quickly and seamlessly integrated into the network router design. The soft processor functions in reconfigurable logic and the microprocessor functions are seamlessly integrated via the Proceler run-time interface.

Proceler Revolutionizes Embedded Design

Through three main avenues, Proceler's technology will revolutionize the way high-performance embedded applications are designed and developed. First, it allows embedded systems designers to build application-specific soft processor through a fast software-based, compiler-driven design flow rather than using a traditional hardware design flow. Second, DVAITA's soft ISA abstraction enables compile times that are comparable to that of state-of-the-art commercial optimizing compilers. Third, DVAITA's soft ISA enables processor customization on a per-program basis, providing maximum flexibility.

A Much More Efficient Approach
Proceler's solution is much more efficient than other ways of accelerating designs. Proceler is the first company to bring to market a completely software-based approach to embedded application design on reconfigurable logic.

The traditional way is to design an ASIC (application-specific integrated circuits) to accelerate a microprocessor's performance. This is an extremely expensive (millions of dollars) and time-consuming (months or years) process requiring hardware design expertise and very expensive design tools. In addition, software must be painstakingly integrated with the hardware, adding time to the development process.

Other solutions for accelerating embedded designs have been proposed by companies who offer custom processing cores. Their process of customization involves the definition of new instructions around a core instruction set and the use of the proprietary vendor tools and extensions to implement the processor datapath. These emerging companies are bringing microprocessor customization to the user. However, this customization is performed at design time. Thus performance trade-offs must be made across a range of applications and the upper limits of performance are fixed at design time. Furthermore, these custom cores lack the ability to leverage COTS software/hardware.

Proceler's technology enables processor customization in a major way by enabling customization at compile time rather than design time. Because DVAITA is a soft ISA, it allows Proceler to define ISAs that are tailored to a specific application domain. While microprocessor ISAs are limited by available silicon area, the use of reconfigurable logic permits the definition of a range of ISAs and the use of any one of these ISAs at a time. Furthermore, the implementation of compute-intensive portions of an application is customized on a per-program basis.

The Proceler development process utilizes standard C or C++ with no proprietary extensions. Therefore, application development can rely on more widely available software engineering skills based on standard, high-level programming languages. Furthermore, because Proceler's soft processors are integrated on an RCS, the application can leverage the on-board COTS microprocessor, which enables the use of COTS real-time operating systems (RTOSs), software, drivers, etc.

The ESC Demo

Proceler will provide the first demonstration of its new technology at the Embedded Systems Conference, April 9-13, 2001, in San Francisco. The demo will show the development flow through a functionally complete set of the features of the tools and generate a target executable. It will show the functioning of the development tools within the framework of the product's release development platform. And it will load the generated executable onto a commercially available RCS platform and run the design.

Proceler, Inc., is the next-generation technology developer for accelerating embedded systems designs. Proceler enables developers to build high-performance, application-specific soft processors on commodity hardware, utilizing an accelerated, standard software development process. Proceler's headquarters is at 2855 Telegraph Avenue Suite 401, Berkeley, CA 94705, Phone: (510) 540-1740.

Source: Proceler Inc.

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