News | June 15, 1999

Synplicity To Show Advanced ASIC Partitioning Tool At DAC

Synplicity,Inc., a supplier of logic synthesis software for programmable logic design, announced that it will demonstrate its advanced synthesis and partitioning tool, called Certify, at the 1999 Design Automation Conference (DAC) in New Orleans, June 21-24. Designed to work with emulation tools such as Aptix's System Explorer, Certify provides a dramatic increase in productivity for designers prototyping large ASICs, especially for multimedia and communications applications. DAC attendees will see the Certify tool partition and synthesize an ASIC into multiple FPGAs to enable this rapid system prototyping.

"Verification is the biggest bottleneck in ASIC design today, and a growing number of designers are turning to FPGA-based prototyping to verify their larger designs before they go to silicon," said Andy Haines, vice president of marketing for Synplicity. "For example, the combination of Certify and Aptix's System Explorer enables customers to quickly build their verification-ready prototypes and begin the complex task of debugging their designs."

When combined with popular industry emulation and prototyping tools such as Aptix's System Explorer, Certify provides a complete ASIC prototyping flow. Over the past year, Synplicity has worked with Aptix to provide a solution to designers verifying system-on-a-chip (SoC) designs. The Certify tool adds unique capabilities to prototyping hardware to implement customer designs more efficiently with higher performance. In addition, Synplicity and Aptix also established a joint marketing and sales arrangement to provide the Certify and System Explorer products to designers developing high-density SoC and ASIC solutions. The Synplicity/Aptix prototyping and verification solution currently supports devices fromAltera and Xilinx.

The Certify tool is an advanced RTL partitioning tool combined with an enhanced synthesis engine. Partitioning in Certify is done at the RTL level and is based on synthesis estimates of area and connectivity, resulting in much higher productivity than current gate-level partitioning approaches. In addition, the Certify tool does not require that the original HDL source code be modified for either observability or partitioning reasons. Verification teams building ASIC prototypes are extremely reluctant to modify the HDL source code, since their primary goal is to validate the functionality of the ASIC. For example, the Certify tool enables the users to replicate logic without making any changes to the HDL source code. This ability is extremely important, because it enables users to minimize the interconnects between the devices on the prototype board, and allows them to achieve higher prototype speed -- something impossible to do using traditional gate-level approaches to partitioning and synthesis.