Cadence And Denali Join Forces

Cadence Design Systems, Inc. and Denali Software, Inc. (Palo Alto, CA) have reached an agreement to integrate Denali's Memory Modeler and Graphical Memory Debugger with the Cadence Affirma family of hardware description language (HDL) logic simulators. This integration allows mutual customers to rapidly generate customized memory models, increasing functional simulation performance of system-on-a-chip (SOC) designs.

The IEEE 1499 Open Model Interface (OMI) was chosen to link the Memory Modeler to the Cadence simulation products because of its extreme flexibility and extensibility. OMI allows model sharing at any level of abstraction and any OMI compliant model can be executed on any OMI-compliant simulator regardless of the language the model is written in. The Cadence Affirma simulators have supported OMI-based integration within the Cadence design environment and for third-party tools since June, 1997.

The Denali Memory Modeler will be integrated with the Cadence Affirma SimVision environment, which is the graphical user interface to the Cadence logic simulators. This will provide customers with a smooth integration flow and a uniform look and feel across Cadence simulator products. The Memory Modeler utilizes Denali's Specification of Memory Architecture (SOMA) language to simplify the design of memory architectures and enable distribution of memory components and cores across the Internet and World Wide Web. The Modeler creates memory components for SOC applications and can be tailored to key memory specifications including DRAM, SRAM, SPRAM, SGRAM, DRR, SSRAM, FLASH, PROM, SEPROM AND FIFO memories.