GPIB-card

The data transfer to or from the GPIB card is performed via two FIFO registers/buffers. The FIFOs are used to decouple GPIB data traffic from the CPU bus. Using the INES GPIB card as an IEEE488.2 device, the FIFOs may be used as the input or output queue what simplifies the software design significantly. In addition, it support the IEEE488.2 Trigger Control and to support the MAV (Message Available) Reset directly in the hardware. The FIFOs may be accessed respectively with simple read and write operations (to the DIR or CDOR). Using this technique combined with repetitive move instructions (i.e., REP INSB of the CPU) allows use of the full band width without using direct memory access.
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