Lint Checker

Verisity Design, Inc.nt checker incorporates race detection and finite state machine (FSM) analysis technology for faster, more efficient checking of design code. It analyzes and debugs designs before simulation, thereby increasing the quality of the design code and catching bugs sooner in the flow. The device fits easily into existing design flows and works with all existing functional verification techniques and Verilog designs. It covers seven classes of rules checks—syntax, standard lint, coding style, simulation, synthesis, FSM, and race detection. These checks help to reduce downstream simulation and synthesis errors and provide a standard consistency measurement for diverse design teams.

<%=company%>, 2041 Landings Dr., Mountain View, CA 94043. Phone: 650-934-6800; Fax: 650-934-6801.