MIPS32 4Kc and MIPS64 5Kc Processors

The MIPS' processor architecture has always been a key component of our embedded strategy. Our compilers and development environment have been optimized to take full advantage of the MIPS processor architecture's superior mix of high performance, low power consumption, and reduced memory usage.

The MIPS32 4Kc (Jade) is a high-performance, synthesizeable, 32-bit RISC processor core optimized for low-power, battery-operated, systern-on-a-chip ASIC applications. Fully compatible with the MIPS32 architecture, Jade supports R3000 and R4000 user-level code and is optimized for running embedded operating systems. The Jade core and its bus interface operate at speeds from 0-200 MHz, consuming just 2 mW/MHz when equipped with 16 kbytes of cache and fabricated in a typical 0.25-micron process. The core features a five-stage pipeline with branch control and single-cycle execution for most instructions, a 32-bit entry MMU, and up to 16 kbytes each of 4-way, set-associative instruction and data cache.

The MIPS64 5Kc (Opal) is a high-performance, synthesizeable 64-bit RISC processor core optimized for low-power, battery-operated, system-on-a-chip ASIC applications. Optimized for embedded operating systems, Opal runs user R4000 and R5000 code, features a peak clock frequency of 375 MHz, and consumes just 1 mW/MHz when fabricated using a typical 0.15micron CMOS process. Opal features a six-stage pipeline with branch control and single-cycle execution for most instructions, a co-processor interface for FPUs, a 64-entry MMU, and up to 64 kbytes each of 4-way set-associative cache.

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