PBT-515 - New 64-bit 66 MHz PCI Bus Analyzer & Exerciser
State-of-the-art in PCI Debugging
The PBT-515 is designed to assist hardware, software and system validation engineers in developing, testing and validating the latest generation 64-bit and 33/66 MHz PCI-based systems. As VMETRO's third generation PCI Analyzer, the PBT-515 offers unprecedented debugging capabilities in a single-slot PCI short card. The PBT-515 is a complete logic analyzer and bus exerciser for PCI buses up to 64-bit wide and at clock speeds up to 66.7 MHz. This new generation tool provides even more system validation tools and exerciser performance then previous tools as well as additional PCI bus analysis features. The unit is operated through USB or RS232 from a PC running Windows and VMETRO's BusViewTM graphical user interface, or via RS232 from an ASCII terminal or terminal emulator. As with all VMETRO analyzers, the unit may be powered from the target system or from an external power supply, and extensive on-line help is available.
FEATURES
State Analyzer
64- or 32-bit PCI up to 66.7 MHz
Clock, Transfer or Transaction Sampling modes
Demultiplexed Address/Data for maximum trigger and store flexibility
64K/256K Trace Buffer
8M Trace Buffer optional with piggyback module
Onboard Exerciser
64- or 32-bit PCI Master & Target up to 66.7 MHz
Built-in script Recording and Playback engine
Exerciser can be started independently of analyzer
8 MB Target Memory, available at all times
Generates PCI Interrupts
Timing Analyzer
500 MHz Timing Sampling of 64 PCI signals
Upper and lower half of 64-bit PCI selectable
16 MSamples Trace Buffer
Anomaly Trigger
Automatically detects 84 PCI Anomalies of 32-bit and 64-bit PCI up to 66.7 MHZ
50ps Timing Resolution on setup and hold time measurements at 66.7 MHz
Expandable with Piggyback Modules
Although the PBT-515 offers a full-featured logic state analyzer with extensive statistics functions as well as a powerful exerciser, the unit can be expanded with piggyback modules (daughtercards) for even more functionality and performance. One such card is the PTIMBAT500-PB, targeted at detailed hardware analysis applications. This module offers a 64-channel 500 MHz Timing Analyzer with 16 MSamples trace buffer, and a comprehensive PCI Anomaly Trigger (protocol checker). In addition to offering a detailed 2ns resolution view with waveform diagrams of the bus timing, this unit provides automatic detection of 84 PCI protocol and timing violations, including 50 picoseconds timing resolution on setup/hold time measurements. Another card, the PXMEM8M-PB, offers an extremely deep trace buffer for the state analyzer, storing as much as 8 million clock, address or data cycles, suitable for statistics gathering or verification applications. (Only one piggyback module can be mounted at a time.)
Minimum PCI Signal LoadingMinimum PCI Signal Loading
The PCI bus has very strict requirements for signal loading and allowable trace lengths on add-on cards. Particularly in 66 MHz systems this is an important issue. For this reason, the PBT-515 has carefully laid-out signal tracks with the shortest possible signal lengths. In addition to the single load represented by the exerciser, there is only one small load of approximately 2pF of ultra-low capacitance buffers in front of the state analyzer and the piggyback expansion connectors.
For analysis in systems with no spare PCI slot, VMETRO offers a special zero-slot adapter which carries the PBT-515 in addition to one PCI expansion board. Compared to other solutions where the bus analyzer acts as an extender card as well, VMETRO's approach avoids the burden of an extra load of the extended PCI signals unless when really needed.
State Analyzer with Various Sampling Modes
The State Analyzer of the PBT-515 captures and displays 64-bit or 32-bit PCI bus activity up to 66.7 MHz with highly advanced (yet simple to use) triggering, filtering and counting capabilities. To provide optimum bus analysis for a given problem, the state analyzer offers a choice of three sampling modes. (A fourth sampling mode being offered by the optional 500 MHz Timing Analyzer).
The Clock sampling mode is a plain "clock-by-clock" sampling mode as found in any state analyzer. Augmented by address and data phase highlighting and command mnemonics, this is highly suitable for low-level hardware oriented analysis of the bus protocol as executed by bus interface state machines.
High-level Bus Sampling
For software and system integration issues, debugging the PCI bus on a clock-by-clock basis is not productive, the user would have to spend time on understanding the bus protocol rather than investigating the actual problem. For this reason, analysis on a higher level is required, with focus on bus traffic rather than the bus protocol. Therefore, VMETRO offers in addition two unique higher level sampling modes, aimed at producing a more meaningful trace for software and system engineers. One such mode is called Transfer Mode, in which the analyzer hides details about the PCI bus protocol for the user, and avoids sampling during idle or wait states. This is done by means of protocol-sensitive bus sampling, de-multiplexing of address/data (for 32-bit data transfers), internally generated utility signals for burst detection etc., and extensive use of mnemonics. This allows the user to focus explicitly on the essential Command, Address, Data and Status values, both in the trigger event specifiers and in the trace display. In addition, the user is given information about time from trigger, time between transactions and transfers, the latency or number of wait states per transaction and whether a transfer is part of a burst or at the start of a burst.
The third sampling mode is called Transaction Mode. This is similar to Transfer Mode except that instead of displaying Data it displays the total Burst Length for each transaction. In this mode, a vast number of PCI transactions are stored in the trace buffer, producing trace that is optimal for system behavior analysis, validation and performance tuning.
Trace Buffer Options
The PBT-515 state analyzer is offered with 64K or 256K samples trace buffer, where each entry represents either a clock cycle, an address or data transfer (for 32-bit data complete with command, address and status values) or a transaction, depending on the chosen sampling mode as described above. In addition, the optional expanded trace buffer piggyback module (PXMEM8M-PB) holds another 8 MSamples which can be either clock cycles or addresses/data transfers (up to 33 MHz). The user may search for data in the trace buffer, as well as extracting only samples of interest for selective display. Traces can be stored to files on the host PC, and the trace buffer can also be compared with a reference trace in files on the host PC. This allows for easy identification of differences between the behavior of faulty and a properly functioning systems.
Advanced Trigger and Store capabilities
The PBT-515 uses VMETRO's unique programming language-like trigger sequencer to specify triggers, store and count and delay qualifiers in an "If-then-else…" fashion. Together with the intuitive demultiplexed sampling method (which puts Command, Address, Data and Status as separate items also in the trigger event specifiers) and true inside/outside range specifiers on address and data fields, the user may easily create sophisticated triggers and store qualifiers without having to use multiple events to define trigger attributes of a single transfer. The user may store his own trigger setups, either in non-volatile memory on the analyzer or on files on the host PC. The analyzer also automatically maintains the current trigger and sequencer setting after power off/on cycling. In sum, all these features allow the user to solve his problem quickly, instead of spending hours trying to figure out how to set up and understand the analyzer.
Statistics
The PBT-515 comes with an extensive set of PCI bus statistics and performance measurement functions. Based on dedicated hardware counters, the analyzer offers real-time Bus Utilization and Efficiency statistics that can run at all times as an active window on the screen, in parallel with bus tracing or exercising. There is also real-time Event Occurrence statistics based on user-defined values in the trigger event recognizers. In addition, measurements of Bus Transfer Rate, Command Distribution and Burst Distribution are done by preprogrammed post-capture analysis of the data in the trace buffer. The user may save the displayed statistics data to an ASCII file, for later data importation into applications such as EXCEL for post processing and display.
All this makes the PBT-515 the Premier State Analyzer and by far the most versatile and user-friendly PCI analysis tool available on the market today.
The PCI bus has very strict requirements for signal loading and allowable trace lengths on add-on cards. Particularly in 66 MHz systems this is an important issue. For this reason, the PBT-515 has carefully laid-out signal tracks with the shortest possible signal lengths. In addition to the single load represented by the exerciser, there is only one small load of approximately 2pF of ultra-low capacitance buffers in front of the state analyzer and the piggyback expansion connectors.
For analysis in systems with no spare PCI slot, VMETRO offers a special zero-slot adapter which carries the PBT-515 in addition to one PCI expansion board. Compared to other solutions where the bus analyzer acts as an extender card as well, VMETRO's approach avoids the burden of an extra load of the extended PCI signals unless when really needed.
State Analyzer with Various Sampling Modes
The State Analyzer of the PBT-515 captures and displays 64-bit or 32-bit PCI bus activity up to 66.7 MHz with highly advanced (yet simple to use) triggering, filtering and counting capabilities. To provide optimum bus analysis for a given problem, the state analyzer offers a choice of three sampling modes. (A fourth sampling mode being offered by the optional 500 MHz Timing Analyzer).
The Clock sampling mode is a plain "clock-by-clock" sampling mode as found in any state analyzer. Augmented by address and data phase highlighting and command mnemonics, this is highly suitable for low-level hardware oriented analysis of the bus protocol as executed by bus interface state machines.
High-level Bus Sampling
For software and system integration issues, debugging the PCI bus on a clock-by-clock basis is not productive, the user would have to spend time on understanding the bus protocol rather than investigating the actual problem. For this reason, analysis on a higher level is required, with focus on bus traffic rather than the bus protocol. Therefore, VMETRO offers in addition two unique higher level sampling modes, aimed at producing a more meaningful trace for software and system engineers. One such mode is called Transfer Mode, in which the analyzer hides details about the PCI bus protocol for the user, and avoids sampling during idle or wait states. This is done by means of protocol-sensitive bus sampling, de-multiplexing of address/data (for 32-bit data transfers), internally generated utility signals for burst detection etc., and extensive use of mnemonics. This allows the user to focus explicitly on the essential Command, Address, Data and Status values, both in the trigger event specifiers and in the trace display. In addition, the user is given information about time from trigger, time between transactions and transfers, the latency or number of wait states per transaction and whether a transfer is part of a burst or at the start of a burst.
The third sampling mode is called Transaction Mode. This is similar to Transfer Mode except that instead of displaying Data it displays the total Burst Length for each transaction. In this mode, a vast number of PCI transactions are stored in the trace buffer, producing trace that is optimal for system behavior analysis, validation and performance tuning.
Trace Buffer Options
The PBT-515 state analyzer is offered with 64K or 256K samples trace buffer, where each entry represents either a clock cycle, an address or data transfer (for 32-bit data complete with command, address and status values) or a transaction, depending on the chosen sampling mode as described above. In addition, the optional expanded trace buffer piggyback module (PXMEM8M-PB) holds another 8 MSamples which can be either clock cycles or addresses/data transfers (up to 33 MHz). The user may search for data in the trace buffer, as well as extracting only samples of interest for selective display. Traces can be stored to files on the host PC, and the trace buffer can also be compared with a reference trace in files on the host PC. This allows for easy identification of differences between the behavior of faulty and a properly functioning systems.
Advanced Trigger and Store capabilities
The PBT-515 uses VMETRO's unique programming language-like trigger sequencer to specify triggers, store and count and delay qualifiers in an "If-then-else…" fashion. Together with the intuitive demultiplexed sampling method (which puts Command, Address, Data and Status as separate items also in the trigger event specifiers) and true inside/outside range specifiers on address and data fields, the user may easily create sophisticated triggers and store qualifiers without having to use multiple events to define trigger attributes of a single transfer. The user may store his own trigger setups, either in non-volatile memory on the analyzer or on files on the host PC. The analyzer also automatically maintains the current trigger and sequencer setting after power off/on cycling. In sum, all these features allow the user to solve his problem quickly, instead of spending hours trying to figure out how to set up and understand the analyzer.
Statistics
The PBT-515 comes with an extensive set of PCI bus statistics and performance measurement functions. Based on dedicated hardware counters, the analyzer offers real-time Bus Utilization and Efficiency statistics that can run at all times as an active window on the screen, in parallel with bus tracing or exercising. There is also real-time Event Occurrence statistics based on user-defined values in the trigger event recognizers. In addition, measurements of Bus Transfer Rate, Command Distribution and Burst Distribution are done by preprogrammed post-capture analysis of the data in the trace buffer. The user may save the displayed statistics data to an ASCII file, for later data importation into applications such as EXCEL for post processing and display.
All this makes the PBT-515 the Premier State Analyzer and by far the most versatile and user-friendly PCI analysis tool available on the market today.
64-bit Exerciser at 33 or 66 MHz
The PBT-515 features a built-in advanced 64-bit PCI Exerciser that functions as a Bus Master interface with DMA, a Target interface with a real 8 MBytes of memory behind it and a PCI Interrupter. The exerciser supports 64- and 32-bit PCI at 33 MHz in the basic model (PBT-515BX), while a 66 MHz exerciser is provided in the high-end models (PBT-515DX and PBT-515EX). The exerciser is controlled with dialog boxes through the user-interface, or self-running with the built-in script recording and playback capability with programmable delay and loop functions.
The Exerciser is a separate functional unit of the PBT-515 board, which can be started and run totally independently and concurrently with the analyzer. Similarly, the Target interface is another separate functional unit with an 8 MByte real memory that can be accessed by other PCI agents at any time, with a base address specified by the user. The BIOS of the host system will not need to initialize the PBT-515.
The Bus Master has as many as four DMA engines, allowing the user to test transactions to several target devices concurrently. Normally, the DMA controllers transfer data between the local memory and PCI memory. However, a unique feature of the PBT-515 Exerciser is the ability to transfer with DMA data from one PCI device to another. Up to 8 MBytes of data can be transferred per DMA command, with peak burst data rates of 533 MB/s (PBT-515DX and PBT-515EX).
A comprehensive set of commands is available to the user to inspect, manipulate and test data in PCI and local memory. There are also commands to load, dump and compare data between PCI or local memory and files on the Windows host PC. Explicit memory test commands are also provided, using data patterns such as random or walking ones/zeros. If an error is found, the exerciser can trigger the onboard state analyzer and the optional 500 MHz Timing Analyzer for immediate review of the failing cycle(s). The module may also generate PCI interrupts, IntAck and Special Cycles on the PCI bus.
These features together with the easy-to-use script recording and playback capability allows the user to build a library of self-running tests stored as files on his Windows host PC. This makes the PBT-515 ideal for running automated tests during design verification or production test of PCI devices, adapters and motherboards.
VMETRO Inc., 1880 Dairy Ashford, Suite 535, Houston, TX 77077. Tel: 281-584-0728; Fax: 281-584-9034.