Synplicity enhances synthesis tool to overcome IP integration barriers

<%=company1%> (Sunnyvale, CA) has enhanced its Synplify Pro synthesis solution to support designers integrating intellectual property (IP) into high-density FPGAs. With this new release, the synthesis product includes support for FPGA designs containing both Verilog and VHDL modules, known as "mixed-language" designs. Additionally, the new release offers support for IP cores whose timing is modeled in the STAMP format, enabling improved timing performance in designs using pre-synthesized IP. Synplicity also announced the Synplify Pro software supports the Xilinx Modular Design Flow. Synplicity has improved quality of results for Xilinx Virtex-II devices and Altera APEX20K/E families while adding new support for devices from Actel, Lattice Semiconductor, Lucent, QuickLogic, and, for the first time, Triscend.

The new Synplify Pro release offers mixed-language support, giving designers the ability to mix Verilog and VHDL modules within a design. Traditionally, a designer would have to manually re-implement an IP module if it were written in a language different from the primary language of the design. The Synplify Pro software enables communication between the modules, eliminating the need to re-implement the IP module. This becomes increasingly important as programmable logic design density increases and design reuse becomes a necessity. This mixed-language support can also benefit a team of designers implementing complex FPGAs by allowing individual designers to work on portions of the design in their language of choice.

The software also includes support for the STAMP modeling format, enabling synthesis to understand timing within IP modules and therefore better optimize its surrounding logic. STAMP is a popular modeling format that is part of Synopsys Liberty program.

The enhanced family of Synplify products includes new quality of results improvements for Xilinx Virtex-II FPGAs, including Dynamic SRL support, automatic inference of Up/Down counters, and support for simultaneous read and write for BlockRAMs. With this release, sequential shift components are automatically inferred and then implemented as an SRL (Shift Register Lookup) table, significantly improving performance in designs using these components.

For the first time, the Synplify Pro software includes support for the Xilinx Modular Design Flow. Using the Synplify Pro product within the Modular Design Flow, design teams can easily define modular boundaries for each team member, and generate separate netlists and constraints for each section of the design. This approach is important for the design of very complex devices where portions of the design must be completed incrementally.

This new release of Synplify software includes several new quality of results improvements for Altera's APEX20K and APEX20KE family of devices including automatic inference of Up/Down counters, improvements for timing optimization, mapping of cascade/carry chains, automatic inferencing or ROMs, and mapping to LPM ROMs and NativeLink support for Unix. Together these improvements provide APEX users with significantly faster performing devices.

For the first time, the Synplify products include support for Triscend's A7 and E5 device families, which offer a configurable SoC solution to address high-performance, customizable SoC applications. Additionally, the Synplify synthesis solutions now offer support for Actel 54SXS and eX families, Lattice SuperFAST and SuperWIDE families, Lucent Orca4 family and QuickLogic QuickDSP family.

The Synplify 6.1 and Synplify Pro 6.1 synthesis solutions are available now. Pricing for the Synplify software starts at $9,000 (U.S.) and pricing for Synplify Pro software starts at $19,000 (U.S.). Current customers on maintenance will be upgraded at no additional cost.

Synplicity Inc., 935 Stewart Drive, Sunnyvale, CA 94085. Tel: 408-215-6000; Fax: 408-990-0290; e-mail: info@synplicity.com.

Edited by David Maliniak
Managing Editor, ElectronicsWeb.com