V3 Semiconductor Introduces New Enhanced PCI (PDF)

The V363EPC is fully compliant with the PCI Local Bus Specification, Revision 2.1. It is available in 50 MHz for both PCI and local bus clock. The V363EPC also features 768 bytes of on-chip FIFOs—this significantly reduces access latencies by handling continuous transfers of large data streams without tying up the local or PCI buses. The Dynamic Bandwidth Allocation™ architecture allows adjustment of the draining and filling strategy of the read and write FIFOs to most efficiently meet the data stream requirements.