Verilog And VHDL Design Checker

Novas Software Inc.design rule checker for Verilog and VHDL. The new tool is integrated with Novas' Debussy Knowledge-Based Debugging system.

nLint helps designers create syntactically and semantically correct HDL code by performing source code checks to ensure conformance with design rules such as synchronous design, clocking scheme, naming conventions and testability.

nLint works standalone as well as with Debussy. The product is available from Novas and on the Toolwire Design Chain Management (DCM) Network. Toolwire is an application service provider offering web-based pay-per-use access to EDA tools and services. Through Toolwire, Verilog and VHDL designers have access to nLint anytime or anywhere through their web browser.

nLint for Verilog ships in May for Unix, Linux, and Windows NT platforms. nLint for VHDL ships in Q4. Pricing is $14,900 for a floating local-area network license. Pay-per-use pricing on the Toolwire DCM Network starts at $9.50 per run in quantities of 100.

The Debussy system automates debug tasks and provides engineers better ways to understand behavioral, RTL, and gate-level designs. nLint complements Debussy by finding potential bugs earlier, before users run simulation, synthesis or test tools.

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