Product/Service

Xtensa III

Source: Tensilica
The Xtensa III release includes a 32-bit single precision floating point coprocessor option optimized for printing
Floating Point Unit

The Xtensa III release includes a 32-bit single precision floating point coprocessor option optimized for printing, graphics and audio applications. The principal objective guiding the design of this coprocessor was to provide the programming ease of floating point at the cost of fixed point processing. It adds the logic and architectural components needed for IEEE 754 single-precision floating-point operations.

Major Features:


  • 16 dedicated floating point registers

  • Full set of load/stores, offset and indexed address update modes

  • Fully pipelined arithmetic operations in hardware:

    • add, sub, mul, madd, msub 4-cycle latency

    • loads and converts: 2-cycle latency

    • moves, compares 1-cycle latency



  • Full compiler support C/C++ float

Performance (0.18-micron, 1.8v):


  • Adds 20-25K gates to base processor for a total of 1.2 -1.5 square mm total core area.

  • Sustains 2 FLOPs/cycle = 400 MFLOPs in 0.18-micron.

Xtensa III, the third generation of Tensilica's breakthrough technology, includes more complete configurability in hardware and software, more powerful features within the Xtensa architecture, and seamless integration of new DSP, control and media processor capabilities into the system-on-chip (SOC) environment. Included are three powerful preconfigured coprocessor options: the Vectra DSP Engine, Floating-Point Unit and a 32-bit multiplier. Xtensa III also includes complete automated methodology for generating designer-defined instructions using an upgraded Tensilica Instruction Extension ("TIE") Compiler, and automated configurability of system development environments and leading third party RTOSes

The Xtensa Processor Features:

  • 16/24-bit Xtensa ISA
  • 200MHz (worst case)/320MHz(typical) performance levels at 0.18um technology
  • 0.7sq mm core area at 0.18um process
  • 0.4mW/MHz core power dissipation at).18um, 1.8V operation
  • On-chip memory architecture including 1,2,3 and 4-way set associative caches; up to 16KB instruction and data caches; up to 256KB data RAM or data ROM; up to 128KB instruction RAM and instruction ROM.
  • OSKit RTOS targeting environment includes support packages for
  • Accelerated Technology, Inc.'s Nucleus and WindRiver Systems' VxWorks for Tornado.
  • Instruction Set Simulator and Bus Functional Model for Mentor Graphics Seamless Co-verification Environment and Synopsys Eaglei Co-verification tool.

TIE Enhancements:

  • Boolean registers: 16 1-bit registers provide for parallel compares and
    conditional moves.
  • Up to four-cycle pipelined instruction capability.
  • Designer-defined register files: A new TIE definition enables multiple
    designer-defined special register files.
  • Wide load/store operations with address update: TIE language allows for
    32/64/128 bit wide load/store operations for efficient memory bandwidth utilization.
  • Register file ID: Designers can specify up to 8 coprocessor Ids for the set of states associated with each coprocessor. By associating a coprocessor ID with each
    register file, "lazy" save and restore operations become possible and are
    utilized for easy and fast context switching.

Software Enhancements:

  • Development tools on Windows NT: The Xtensa processor is delivered with a
    rich set of software development tools. These tools are now available on Windows NT 4.0 as well as Solaris. The tools include an instruction set simulator and a GNU-based compiler, linker and assembler.
  • Enhanced compiler support: Xtensa's software development environment is
    fully integrated with the processor configuration system, supporting ANSI C and C++ code with configuration-specific language extensions. The compiler now allows the user to add configurable types to support easy programmability and automatic register allocation of user-defined coprocessors and register files. Aggressive optimization includes constant propagation, common subexpression elimination, loop invariant code motion, loop unrolling, global data flow analysis, instruction scheduling, local and global register allocation and jump optimization.

Tensilica, 3255-6 Scott Blvd., Santa Clara, CA 95054. Tel: 408-986-8000; Fax: 408-986-8919.